The Lattice HetNet Solutions Portfolio provides a portfolio of programmable solutions for building smart, low-power cellular equipment needed to support the global rollout of Heterogeneous Networks (HetNet). Announced today, the Portfolio will allow system designers to implement best-in-class solutions for connectivity, control path and power management while accelerating their development with system-level reference designs for multi-mode LTE small cell.
The Lattice HetNet Solutions Portfolio enables designers of small cells, low-power remote radio heads, distributed antenna systems, and active antennas, to achieve the lowest BOM, power consumption and smallest footprint for the connectivity, control path and power management functions of their systems. Complementing the ASICs and SOCs used for complex data path functions, Lattice’s industry leading FPGAs, CPLDs and programmable power management devices meet requirements for small form factor, low-cost and ultra-low power.
“FPGA technology like LatticeECP3 devices which can support key connectivity interfaces such as CPRI, JESD207 and others in a small, low-power footprint, are a major enabler for a new generation of mobile infrastructure equipment,” said Ajit Singh, CEO at Azcom Technology. “Hardware programmability to cope with the many interoperability requirements and complex network environments is a must for developers as the HetNet market continues to evolve.”
Combined with soft IP for connectivity, control path and data path functions optimized for low complexity HetNet applications, the LatticeECP3, MachXO2™ and MachXO3™ FPGA families, Lattice power management devices and Azcom reference platform give developers everything they need for affordable innovation of HetNet systems. Specific elements of the HetNet Solutions Portfolio include:
The Lattice HetNet Solutions Portfolio is supported by the Lattice Diamond software. Optimized for Lattice’s low and ultra-low density FPGAs, the software comprises leading-edge design and implementation tools optimized to allow electronic system designers to meet their power, size, and cost goals.