HiSilicon and imec collaborate on reconfigurable RF transceivers

28th February 2012
News Release from: IMEC
Written by : ES Admin
HiSilicon and imec have signed a strategic research collaboration to develop innovative RF transceiver architectures for next-generation mobile terminals. With the partnership, HiSilicon joins imec’s R&D program on cognitive reconfigurable radio to jointly conceive low-power and compact high-performance reconfigurable RF transceivers leveraging on state-of-the-art CMOS technology.
Imec’s cognitive reconfigurable radio front-end program investigates reconfigurable RF solutions, high-speed/low-power analog-to-digital converters (ADCs) and new approaches to digitize future RF architectures and minimize antenna interface requirements. By combining fundamental rethinking of the circuit architectures and designs with clever use of the benefits that the aggressively scaled technology offers (such as high intrinsic speed of the nanoscale transistors) the program aims at developing small, cost-, performance- and power-competitive reconfigurable radio transceivers in 28nm digital CMOS technology covering all key broadband communication standards including next generation cellular and connectivity standards such as LTE advanced and next-generation WiFi (802.11ac).

We are excited to welcome HiSilicon as one of the world’s leading IC design companies and we are honored with this commitment. The new partnership with HiSilicon reflects the value that imec brings to its industry partners in this RF research program; said Liesbet Van der Perre, Director Green Radio program line at imec. We are looking forward to a close cooperation with the HiSilicon research team to develop together our upcoming generation of breakthrough RF designs.”

Mr. Chen Zhen, Director of HiSilicon wireless chipset infrastructure architecture and system design dept. “We expect imec to keep on bringing innovative solutions that will be essential to develop our next generation multimode products. We hope that together with imec, we will realize innovative transceiver architectures utilizing the advantages of new technologies (28nm CMOS and beyond). We expect these solutions can drastically improve the performance while reducing area and power consumption.”

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